1. Technical Field
The present invention relates to a multi-processor system and method and, more particularly, to a multi-processor system having a shared program memory and a related method for allocating identification numbers to the processors in such a system.
2. Related Art
A multi-processor system is generally used for parallel processing. In the multi-processor system, a plurality of processors may perform the same task or different tasks.
Recent designs suggested in the art are exemplified by U.S. Pat. No. 5,655,102 to Galles, entitled System And Method For Piggybacking Of Read Responses On A Shared Memory Multiprocessor Bus, U.S. Pat. No. 5,634,037 to Sasaki et al., entitled Multiprocessor System Having A Shared Memory With Exclusive Access For A Requesting Processor Which Is Maintained Until Normal Completion Of A Process And For Retrying The Process When Not Normally Completed, U.S. Pat. No. 5,581,734 to DiBrino et al., entitled Multiprocessor System With Shared Cache And Data Input/Output Circuitry For Transferring Data Amount Greater Than System Bus Capacity, U.S. Pat. No. 5,579,504 to Callander et al., entitled Multi-Processors Computer System Having Shared Memory, Private Cache Memories, And Invalidate Queues Having Valid Bits And Flush Bits For Serializing Transactions, U.S. Pat. No. 5,469,549 to Simpson et al., entitled Computer System Having Multiple Asynchronous Processors Interconnected By Shared Memories And Providing Fully Asynchronous Communication Therebetween, U.S. Pat. No. 5,448,716 to Hardell Jr., et al., entitled Apparatus And Method For Booting A Multiple Processor System Having A Global/Local Memory Architecture, U.S. Pat. No. 5,440,698 to Sindhu et al., entitled Arbitration Of Packet Switched Busses, Including Busses For Shared Memory Multiprocessors, U.S. Pat. No. 5,297,265 to Frank et al., entitled Shared Memory Multiprocessor System And Method Of Operation Thereof, U.S. Pat. No. 5,289,588 to Song et al., entitled Interlock Acquisition For Critical Code Section Execution In A Shared Memory Common-Bus Individually Cached Multiprocessor System, U.S. Pat. No. 5,289,585 to Kock et al., entitled Multiprocessor System Having A System Bus For The Coupling Of Several Processing Units With Appertaining Private Cache Memories And A Common Main Memory, and U.S. Pat. No. 4,674,033 to Miller, entitled Multiprocessor System Having A Shared Memory For Enhanced Interprocessor Communication.
As explained in more detail below, in such a multi-processor system, the individual processors are directly connected to both local memories and program memories, but are commonly connected to a global memory through a system bus.
This leads to a disadvantage and inefficiency in such a multi-processor system in that, due to the fact that dedicated local memories and program memories are provided for each processor, there is a waste of installation space and inefficiency in cost. This is particularly burdensome in certain cases, such as in a case of a VME system, in which a plurality of processors, local memories and program memories are necessarily installed in a small, restricted space (for example, in the space of a VME board). As also explained below, auxiliary boards can be used to solve this problem but such a technique does not have sufficient reliability to meet certain strict standards (such as the miliary standard specification).